Discrete devices such as MOS transistors are widely used as switching devices in integrated circuits. As integrated circuits become more and more integrated, MOS transistors are increasingly scaled down. As a result, the channel length of each MOS transistor is reduced and this reduction may cause short-channel effects. To inhibit short-channel effects, the junction depth of source and drain regions of the MOS transistor as well as the thickness of the gate insulating layer are typically reduced. However, the reduction of the junction depth and the gate insulator thickness increases resistance (R) and capacitance (C) of the gate electrode. In this case, an electrical signal, which is applied to the gate electrode, is transferred more slowly due to a resistance-capacitance (RC) delay time. In addition, the sheet resistance of the source and drain regions increases because of their shallow junction depths, lowering drivability of the short channel MOS transistor.
To address these problems, a self-aligned silicide (salicide) process is widely used to implement a high performance MOS transistor suitable for the highly integrated semiconductor device. The salicide process is a process technology for reducing electrical resistance of the gate electrode and the source and drain regions by selectively forming a metal silicide layer on the gate electrode and the source and drain regions. A cobalt silicide layer, a titanium silicide layer, or the like is being widely adopted as the metal silicide layer. In particular, the resistance of the cobalt silicide layer has much less dependency on a change in line width. Accordingly, a technology for forming a cobalt silicide layer on the gate electrode of the short channel MOS transistor is being widely used.
One example of a cobalt-disilicide process is disclosed in U.S. Pat. No. 5,449,642 to Tan et al. Another method of forming a cobalt silicide layer is disclosed in U.S. Pat. No. 5,989,988, to Linuma et al. However, when the gate electrode has a width of less than about 0.1 μm, the cobalt silicide layer has a limitation in its application due to a phenomenon known as agglomeration. To address this limitation, nickel salicide processes are being used to manufacture high-performance MOS transistors. A nickel silicide layer may be formed at a relatively low temperature, but may also have poor thermal stability.
The salicide process includes a silicidation annealing process. Typically, a rapid thermal process (RTP) is employed as the annealing process. The RTP performs annealing at a high temperature in a short period of time to solve problems such as the diffusion of unwanted impurities. However, in the RTP, a substrate is heated by radiation from a light source lamp such as a tungsten halogen lamp, and a small change in the radiation affects temperature distribution in the substrate. Further, a desired annealing temperature may not be carefully maintained. Temperature fluctuations may occur more severely as the annealing temperature becomes lower.
Accordingly, it may be improper to use the RTP with the radiation scheme in order to form the silicide layer such as the nickel silicide layer, which is formed at the last process, of which the quality is sensitive to the annealing temperature. That is, application of the RTP to formation of the nickel silicide layer, which entails rapid lamp rate and undesirable annealing temperature fluctuation, may cause defects on the layer surface and in turn it may deteriorate the electrical characteristics of the semiconductor device having the nickel silicide layer.